RISC-V /Debug /Supervisor Context (64-bit scontext)

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Interpret as Supervisor Context (64-bit scontext)

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Description

This optional register is only accessible in S/HS-mode, VS-mode, M-mode and Debug Mode.

Accessibility of this CSR is controlled by mstateenzero[57] and hstateenzero[57] in the Smstateen extension. Enabling {csr-scontext} can be a security risk in a virtualized system with a hypervisor that does not swap {csr-scontext}.

Fields

data

Supervisor mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context.

An implementation may tie any number of high bits in this field to 0. It’s recommended to implement 16 bits on RV32 and 32 bits on RV64.

Links

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